Programmable memories have been implemented using non-volatile memory (NVM) cells with each cell storing a bit of data. These programmable memories can be implemented as stand-alone memory integrated circuits or can be embedded within other integrated circuits.
During operation, data stored within NVM cells can include errors. As such, many NVM systems use error correction code (ECC) routines to improve performance. For example, for multi-bit data located at a given address within the NVM system, an ECC routine is applied to the multi-bit data to generate ECC data that is stored within the NVM system and associated with the multi-bit data. When this multi-bit data is subsequently read from the address location, the ECC routine is performed again to re-generate the ECC data for the multi-bit data. The re-generated ECC data is then compared to the original ECC data to determine if there are bit errors associated with the data stored at that address. For example, ECC routines can be employed that can identify and correct single-bit errors and that can identify but not correct double-bit errors. Further, for such ECC routines, errors including three or more bits can be inaccurately detected as single-bit or double-bit errors or no errors.
For some applications where read failures can cause catastrophic results, it is desirable to detect uncorrectable read failures that have not yet occurred but are likely to occur in the near future. Identifying NVM cells associated such imminent read failures allow these read failures to be avoided thereby avoiding potential catastrophic results for sensitive applications.